1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for affecting wafer process flow based upon fault detection analysis.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control application, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on multiple die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a typical flow of processes performed on a semiconductor wafer 105 by a semiconductor manufacturing system is illustrated. A manufacturing system processes a group of semiconductor wafers 105 (block 210). The manufacturing system may then generally acquire metrology data relating to the processed semiconductor wafers 105 (block 220). The acquired metrology data is then analyzed for process errors and/or errors on the processed semiconductor wafers 105 (block 230). Additionally, the manufacturing system may perform fault detection relating to the processing of semiconductor wafers 105 (block 240). The fault detection data is then analyzed for any faults that may have occurred during processing of the semiconductor wafers 105 (block 250).
The analyzed metrology data may then be used to perform feedback corrections in order to improve the accuracy of the processes performed on subsequent semiconductor wafers 105 (block 260). Additionally, the manufacturing system may adjust the process operation based upon the fault detection data analysis (block 270). The manufacturing system may then perform subsequent processing of semiconductor wafers 105 (block 280).
Among the problems associated with the current methodology is a lack of efficient verification of the faults that are detected. In addition, the errors detected by analyzing the metrology data may contain inherent errors, such as calibration errors that may not be validated properly. However, the analysis relating to the fault detection and the metrology data is generally used to modify and control previously scheduled process flow operations. This may result in inefficient routing of semiconductor wafers 105 throughout a manufacturing facility associated with the manufacturing system. The current methodologies may result in processed semiconductor wafers 105 that may contain lower yields and quality results. Generally, the process flow may be adjusted in a manual fashion in response to the analysis of metrology data or fault detection data. This may lead to inefficient verification of process errors and faults.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for the determination of a process flow based upon fault detection. A process step upon a workpiece is performed. Fault detection analysis based upon the process step performed upon the workpiece is performed. A workpiece routing process is performed based upon the fault detection analysis. The wafer routing process includes using a controller to perform a non-standard process routing.
In another aspect of the present invention, a system is provided for the determination of a process flow based upon fault detection. The system includes a processing tool to process a workpiece. The system also includes a process controller operatively coupled to the processing tool. The controller is capable of performing a workpiece routing process based upon a fault detection analysis. The wafer routing process includes performing a rework process routing, a non-standard process routing, a fault verification process routing, a normal process routing, and/or a termination process routing, based upon the fault detection analysis.
In another aspect of the present invention, an apparatus is provided for the determination of a process flow based upon fault detection. The apparatus includes a process controller adapted to perform a workpiece routing process based upon a fault detection analysis. The workpiece routing process includes performing a rework process routing, a non-standard process routing, a fault verification process routing, a normal process routing, and/or a termination process routing, based upon the fault detection analysis.
In yet another aspect of the present invention, a computer readable program storage device encoded with instructions is provided for the determination of a process flow based upon fault detection. A computer readable program storage device encoded with instructions that, when executed by a computer, performs a method, which comprises: performing a process step upon a workpiece; performing fault detection analysis based upon the process step performed upon the workpiece; and performing a workpiece routing process based upon the fault detection analysis. The workpiece routing process includes using a controller to perform at least one of a rework process routing, a non-standard process routing, a fault verification process routing, a normal process routing, and a termination process routing, based upon the fault detection analysis.